CVE-2025-45006

critical · 9.1

Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.

9.1

CVSS

0.4%

EPSS (exploit prob.)

35th

EPSS percentile

2025-07-01

Published

CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:H

Weaknesses

CWE-266

References

https://github.com/chipsalliance/rocket-chip.git
https://github.com/heyfenny/Vulnerability_disclosure/blob/main/RISCV/Rocket-chip/CVE-2025-45006/details.md
https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications#ISA-Specifications

Query this programmatically:

curl https://evil-db.io/api/v1/cve/CVE-2025-45006